Figure 1

(a) Schematic diagram of the Interspike interval Recognition Unit (IRU). The IRU will respond with an output spike if it is tuned to detect the input interspike interval T. The key circuit elements of the IRU are, (1) a spike selection unit (SSU), whose function is to split the incoming spike train into sequence of individual spikes to be fed into the downstream IRU circuitry, (2) a time delay unit (TDU), which can produce a delayed spike output at time t₀ + t(R) in response to input spike at time t₀, tuned through either an excitatory or inhibitory spike timing dependent learning rule, (3) a detection unit (DU), which triggers a spike output if it receives coincident spike input through the TDU. (b) Schematic circuitry for the IRU constructed with a TDU that can be tuned through spike timing dependent plasticity of an inhibitory synapse (iSTDP). (c) Schematic diagram of the IRU constructed using a TDU that can be tuned through spike timing dependent plasticity of an excitatory synapse (eSTDP).